Cadence Academic Network

About the Cadence Academic Network

"The academic network was launched by Cadence in 2007. The aim was to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems."




Layout practical exercises in DIAS I

In the framework of our course „Design of Integrated Analogue Circuits I“, we offer a series of lectures with practical exercises concerning the topic “layout”, given by Prof. Scheible.

The layout lectures cover all basic knowledge like fabrication steps, representative processes, layout of elements, principles of symmetry and matching, failure mechanisms and preventive measures, as well as topics concerning the layout design flow: design styles, design and verification steps and strategies.

The practical exercises consist of two self learning tutorials and five exercises:

Tutorial 1: ”Polygon Pushing”,

Tutorial 2 “Schematic Driven Layout”,

Exercises: Layout of a NMOS Transistor, Layout of a PMOS Transistor, Simulation and Layout of an Inverter, Layout of a Temperatur Sensor Circuit, Improvement of a DRC ruleset.

All layouts are to be finished DRC and LVS clean. During the practical layout exercises the students work in the Cadence-DFII-Environment using the schematic driven layout flow based on these tools: Virtuoso-Schematic-Editor, Virtuoso-Analog-Design-Environment and Virtuoso-Layout-Editor XL, the simulator Spectre and the verification package Assura for DRC and LVS.  


Practical Exercises: Project „Chip Design

In our student project „Chip Design“ the students get the opportunity, to design their own integrated circuits, to simulate, to layout and verify them, and on top they are fabricated in the Bosch factory and can thereafter be measured with modern measuring equipment at the RBZ. The project is conducted analogue to an industry project including the same staff structure, where the assistants and professors do only play the role of consultants. Each semester a new chip is designed and fabricated and as EDA tool the Cadence Software Virtuoso is used.

This unique opportunity is facilitated by the Robert Bosch GmbH.





The rbz uses Cadence-Software in his courses. In the research projects, we also work with Cadence, even on developer's level.


Research project “Schematic Driven Layout Modules”

As physical design automation for analog ICs is still lagging behind its digital counterpart, parameterized cells are a practicable approach to increase layout efficiency in analog IC design. These so-called “pcells” are used to automatically generate customized but deterministic layouts, typically for basic devices like transistors or diodes.

In this EDA research project, we deal with the development of more complex “module pcells” as well as their seamless inclusion into a schematic-driven design flow. Module pcells are able to create layouts for entire circuit structures, consisting of multiple devices as well as their interconnections. Thanks to the parametrization, module pcells can be implemented flexible enough to cover the variability in circuit and layout which is characteristic of analog design and has been an obstacle for automation approaches ever since.


Research project ”MHz-Converter”

Research project “Power Semiconductors”




Prof. Dr.-Ing.

Jürgen Scheible


+49 (0)7121 / 271-7089