05.07.2016 - "Substrate extraction tool accounting for parasitic BJTs in Smart Power ICs"

Kolloquium am rbz Reutlingen


Im Rahmen der Kolloquiums-Reihe am rbz Reutlingen findet folgender Vortrag statt:


Thema: "Substrate extraction tool accounting for parasitic BJTs in Smart Power ICs"

Referent: Pietro Buccella von der École Polytechnique Fédérale de Lausanne (EPFL)

Termin: Dienstag, 5. Juli 2016, Beginn 16:00 Uhr

Wo: rbz-Standort Reutlingen, Oferdinger Str. 50, 72768 RT-Rommelsbach



The actual IC design flow involves a large number of tools for the design of an IC, starting from initial design conception to the final production. Before the production, it is often required to simulate the circuit with parasitic elements to accurately predict real effects in silicon. Parasitics are extracted from the metallization routing layers of the chip and from RC parasitics of the silicon substrate. For this purpose, specific tools are provided for the substrate extraction and detection of parasitic couplings in ICs.

For high voltage integrated circuits, such as Smart Power ICs for the automotive electronics, it is important to consider the additional substrate parasitic couplings caused by the activation of the parasitic bipolar transistors (BJTs). In this case, existing tools and models can no longer be relied upon to simulate coupling effects caused by the injection of currents into the substrate through forward biased PN junctions with the consequent activation of parasitic BJTs. Therefore, the design flow alone is no longer capable of tracking possible design failures in complex Smart Power ICs which are caused by substrate current couplings.

In this work, we  present an innovative substrate extraction methodology based on a novel SPICE-based substrate model made of interconnected devices which emulate parasitic BJTs. Moreover, the extraction tool provides a means to back-annotate the substrate parasitics with the circuit in one unified solution with conventional design tools. This substrate extraction tool  is built on top of commercial IC design tools making it perfectly suited to IC design engineers.